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Product Descriptions

IRIS304 is a single-chip RF transceiver supporting both TD-SCDMA/HSPA (3G) and GSM/GPRS/EDGE(2.5G) standards. Housed in a 5*5 mm2

81-pin BGA package its footprint is 30% smaller than its predecessor IRIS305. Further footprint/BOM reduction is supported by 3 auxiliary reference clock outputs usable as reference for other radios. 

In 3G mode high sensitivity, linearity and low EVM are among the receiver’s salient features that secure excellent performance in QPSK and 16QAM modes. It offers a unique SAW-less mode to remove both the cost and sensitivity loss of Rx SAW filters, enabling an unprecedented integration level for the RF subsystem. 

The transmitter offers low EVM to support 16QAM used in HSUPA for high throughput, and keeps spurious emissions low to relieve the RF sub system equally of the SAW filters commonly found in TD-SCDMA transmitters.

In GSM/EDGE mode, the receiver excels in low power consumption, in addition to low noise figure and high linearity. Standby time, crucial to user satisfaction, can be improved substantially with IRIS304. The transmitter offers high spectral purity that again enables tough spurious emissions requirements to be met without interstage SAW filters. IRIS304 enables a 2G/3G dual mode RF subsystem to be constructed with a minimum number of components on a very small PCB footprint. 

IRIS304 comes fully integrated with synthesizer and loop filter, A/D and D/A converters, a DCXO, a DCDC-converter, LDO regulators, and two serial peripheral interfaces. Most of the circuits are shared between GSM/EDGE and TD-SCDMA/HSPA modes to achieve a small overall chip size.

Product Features

? Triple-band RF transceiver for TDSCDMA, TD-HSDPA and TD-HSUPA 

? Quad-band RF transceiver for GSM, GPRS and EDGE 

? No SAW filters required for TDSCDMA/HSPA receive path 

? No SAW filters required for TDSCDMA/HSPA transmit path 

? No SAW filters required for GSM/GPRS/EDGE transmit path 

? Fully integrated frequency synthesis, complete with loop filter 

? Integrated DCDC-converter and LDO linear regulators 

? On-chip DCXO 

? Auxiliary DAC for optional AFC support for off-chip TCXO 

? Four reference clock outputs with independent enable pins 

? Auxiliary ADC for measurement of internal or external temperature sensor 

? Support for GGE PA ramping 

? Single or dual SPI control; support for four-wire read protocol on SPI2 

? Parallel digital IQ data interface for TDSCDMA/HSPA 

? DigRF v1.12 data interface for GSM/GPRS/EDGE 

? Optional analog IQ interface (pins shared with TD parallel data interface)

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